This invention relates generally to semiconductor structure manufacturing methods and more particularly to methods used for providing isolated regions within semiconductor structures.
As is known in the art, it has been suggested that bipolar and metal oxide semiconductor (MOS) monolithic integrated circuit chips, or semiconductor structures, use oxide or dielectric isolation, as distinguished from junction isolation, to provide electrical isolation between devices formed in such chips. The main advantages offered by oxide isolation, namely lower parasitic circuit capacitance and potentially greater packing density, result in faster circuits of greater computing power on a given chip size than can typically be achieved using junction isolation.
A variety of methods have been suggested to provide oxide isolation in silicon structures. Common to such methods is the use of a composite silicon dioxide-silicon nitride layer used as a mask for selective oxidation of the exposed surfaces of a silicon structure. The thermally grown or deposited silicon dioxide layer (400-2500.ANG. thick) is formed under a later deposited silicon nitride (500-2000.ANG.) layer. The silicon dioxide layer is used as a buffer layer to absorb some of the stresses developing between the silicon nitride and the silicon substrate due to mismatch of their thermal expansion. To fabricate the oxide isolation, windows are first etched by conventional photolithography and wet or plasma etching into the composite silicon dioxide-silicon nitride layer to delineate the regions where the isolation regions are to be formed. Next, the exposed silicon substrate is etched by isotropic or anisotropic etching to a depth approximating one-half the thickness of the desired silicon dioxide isolation (typically 3000-20,000.ANG.) so that a nearly planar surface is obtained after the step that follows, namely thermal oxidation of the exposed silicon. The nearly planar surface results because about twice as much silicon dioxide is formed as silicon consumed in the oxidation process. One may omit the silicon etching step if a topography where about one-half of the thickness of the oxide isolation rises above the original substrate surface can be tolerated. After the oxidation, the silicon dioxide-nitride masking layer, or nitride part alone, may be stripped and devices such as transistors, resistors, and diffused interconnects may be formed in the islands that were defined by the silicon nitride mask.
While this scheme of forming lateral oxide isolation is generally satisfactory for forming oxide isolation regions in p-type silicon epitaxial layers which are formed on n-type silicon substrates, it needs to be modified for forming isolation regions in n-type epitaxial layers formed on p-type silicon substrates due to the positive charges that always reside in silicon dioxide on silicon, although in various amounts (depending on the processing conditions). If the substrate doping is less than 10.sup.17 atoms/cm.sup.3 as is usually the case, the positive oxide charge may lead to an electrical inversion of the surface of the p-substrate, which thus becomes n-type. This so called n-type channel electrically connects the n-regions of the circuit components with each other which otherwise would have been isolated from each other by the oxide isolation in the lateral direction, and by a reverse biased p-n junction in the vertical direction. In addition to charges in the oxide, interconnects crossing the oxide isolation can induce inversion in substrates of both n or p type polarities, depending on the sign and magnitude of their electrical potential.
In order to prevent loss of isolation by inversion, one usually enhances the substrate doping in a shallow region under the oxide isolation. This can be done using the following methods: Method (1)--the additional doping is selectively introduced into the substrate surface by thermal diffusion or ion implantation. An epitaxial layer is then deposited in which oxide isolation regions are formed, as described above, registered with the enhanced doping pattern; Method (2)--after forming the oxide-nitride mask for selective oxidation, the exposed substrate surface is selectively implanted, or thermally diffused with the anti-inversion layer before the isolation oxide is grown over the same regions. The surface is etched back before the doping takes place if a nearly planar surface after oxidation is desired; Method (3)--this is a modification of method (2) and uses a self-aligned positioning of the enhanced doping under the bottom of the oxide isolation while the sidewalls of the oxide isolation are shielded against it. This is accomplished by creating a mask overhang by etching into the substrate with isotropic or a combined anisotropic-isotropic etch, and then implanting the dopant using the overhang as a shield as described in my U.S. Pat. No. 4,187,125 issued Feb. 5, 1980 and assigned to the same assignee as the present invention.
Due to elimination of registration difficulties, methods (2) and (3) have particular appeal for highly integrated circuits because of their small feature sizes. However, with epitaxial layers and oxide isolation getting shallower (less than 2 micro-meters) in order to obtain faster and smaller circuits, a problem with small breakdown voltages and relatively large parasitic capacitances arises due to the narrow spacing between the heavily doped source and drain regions of MOS transistors, or base region of bipolar transistors, and the rather heavily doped anti-inversion zone. While method (3) significantly alleviates this problem, the spacing it provides may not be large enough for some applications such as PROM's, A/D converters or buffer stages where relatively large breakdown voltages (e.g. 15-50 volts) are often required.